As a semiconductor devices are desired to have higher density integration, a circuit design technology due to a scaling rule has been developed to accommodate a smaller size. As large scale integration in a semiconductor device, such as a DRAM in particular, is continuing to develop a size reduction, a scaling rule of circuit design is remarkably significant.
In order to realize higher density and larger scale integration in a device chip, a redundancy technique has been developed. This technique allows recovery from a defective area in the device chip by substituting the defective area with a redundant circuit provided provisionally.
From a practical perspective, it is difficult to manufacture a LSI memory device without defective memory cells. In an ordinary semiconductor storage device, defective memory cells are identified by a die sorting test and then the defective memory cells are substituted by redundant portions.
As the capacity of a semiconductor device increases, defective bits in the semiconductor device also increase. As a result, it is necessary to increase a number of fuses for relieving the defective bits. In order to obtain a required manufacturing yield rate, it is necessary to relieve the defective bits below predetermined numbers by the fuses In practice, at least several hundreds of defective bits may be relieved by the fuses.
For example, in a large capacity DRAM, about 10,000 fuses are provided in the device chip. When a storage capacity of the device chip increased twice as much under the same design rule, the chip area is also doubled. Thus, physical effects caused by a substance such as small dusts on memory cells become significant. As a result, the defective bits may Increase. Further, as a scaling rule of circuit design proceeds, the same dust can cause more semiconductor elements to be defective. Consequently, the defective bits increase.
In order to substitute the defective area with a redundant circuit, nonvolatile memory elements, such as fuse circuits, are provided preliminarily in the device chip. The specified fuse circuit corresponding to the defective area is blown out by irradiating the fuse circuit with a laser beam. Consequently, only the specified fuse is cut off.
FIG. 7 is a perspective view showing a structure of fuses provided in a conventional semiconductor device. In FIG. 7, four fuses F51 to F54 are formed in the structure. Fuses F51 and F53 are cut off by irradiation with a laser beam, on the other hand fuses F52 and F54 are not cut off and are still intact.
The fuses F51 and F53 blown out by the laser irradiation are used for, for example the storage state, “1”. On the contrary, fuses F52 and F54 are used for, for example the storage state, “0”. By storing the stage state of “1” or “0” in the four figures, it is possible to store the fourth power of 2, i.e., 16 bits in the device.
It is considered that an area of fuses may be reduced by reducing a size of a fuse. However, because of a limitation to a precision of focal position of laser irradiation by a laser used for blowing a fuse and a constraint in a spot diameter of a laser beam, it is difficult to set the laser beam narrower than a certain width. Thus, further reducing an area of fuses would be difficult.
U.S. Patent Application Publication No. 20020125576 discloses a semiconductor storage device having a smaller fuse area. In this semiconductor storage device, a thickness of each fuse is varied by changing irradiation conditions such as irradiation energy or irradiation time.
Since a resistance value of a fuse is inversely proportioned to the thickness of the fuse, the thicker the fuse is, the smaller its resistance value is. Further, the thinner the fuse is, the larger its resistance value is. Bit information is defined corresponding to various resistance values of the fuses. By changing the thickness of a fuse and its resistance value, it is possible to obtain multiple-valued information more than three bits from the fuse element.
FIG. 8 is a perspective view of arrangement of four fuses F61, F62, F63 and F64 in a conventional fuse elememt F60. A laser-irradiated portion 51 of first fuse F61 is removed by laser irradiation such that only end portions 52 of fuse F61 remains. In this state, for example, “0” information is stored in the fuse. The laser irradiated portion 51 of second fuse F62 has comparatively thicker thickness than that of first fuse F61, and third fuse F63 has comparatively thinner thickness than that of second fuse F62. On the other hand, a fourth fuse F64 is not irradiated. In fuse element 60, four resistance values are formed in a stepped manner. In this manner, four bits per one fuse are provided, and it is possible to store the fourth power of 4, i.e., 256 bits in the fuse element of the device. Thus, the fuse area of the device may become smaller than that of the binary system.
However, the multiple-value technique mentioned above requires employment of various laser irradiation conditions, which are difficult to achieve. Accordingly, it is difficult to perform a redundancy in a device with lower cost and higher repeatability.